Intel patents stacked fork-plate transistors, or for 2nm, 20A and other advanced processes

2022-07-17 0 By

It is reported that Intel may once again focus on transistor design research, in order to accelerate the emergence of 2nm and below chip manufacturing process.A recent approved patent shows that Intel has developed “Stacked Forksheet Transistors.”It is understood that the patent application was filed by Intel’s Component research group, indicating its interest in developing chips that are faster and do more with the same amount of power.In addition, Intel’s stack fork-plate transistors enable vertically stacked 3D CMOS structures.The design is described as a transistor device that uses a stack of vertical semiconductor channels near the edge of the trunk, a second transistor stacked on top of the first transistor, and a second transistor similarly stacked with vertical semiconductor channels adjacent to the trunk.Figure type transistor fork plate | stack perspective illustration (source: United States patent database FPO), however, from the patent document and can’t see enough technical details, Intel also fails to submit the reference PPA (power, performance and area, power, performance, and size) to improve data.It is known that the stacked fork-plate transistor is mainly a combination of nanoribbon transistor and germanium atom film.The germanium atom film acts as a Dielectric Wall, which physically separates the vertically stacked transistors and acts as an insulator between the P-gate groove and the N-gate groove.In this design architecture, NMOS (N-metal-oxide-semiconductor) and PMOS (Positive Channel Metal Oxide Semiconductor,P-oxide-semiconductor transistors will be packed more tightly together, leaving more room, but their respective functions will not be affected.Stacked fork-plate transistors are also difficult to reduce in size compared to the most advanced three-gate transistors available today, but the design allows for an increase in the number of transistors.With this stacked transistor technology, Intel can not only pack more transistors into a chip, but also make the chip send signals in three dimensions, rather than the two dimensions used on current chips, allowing transistors to communicate more quickly with each other.Intel showed off the stacked transistor technology at the International Electron Devices Meeting (IEDM) back in 2019, when it was still under development.However, the company has yet to release data on the performance, density and efficiency of its stack fork-plate technology.In fact, Intel isn’t the only company working on stacked fork technology.In 2019, a research group at the Interuniversity Microelectronics Centre (IMEC) in Belgium posted a document online describing a transistor for a related technology they called a stacked fork-plate transistor.IMEC’s transistors offer a significant increase in transistor density when applied to 2nm chips compared to conventional transistor technology.At constant frequency, the stacked fork-plate transistor is 10 percent faster, 24 percent more energy efficient and 20 percent smaller in cell area, the data show.In addition, Static Random-access Memory (SRAM), which is typically used for on-chip caching, will take up 30 percent less space, one of the main “members” that make up the chip’s total area.This indicates that stacked fork transistor technology can improve the performance of the chip at 2nm and below process nodes.Intel and IMEC have a long and close relationship with each other in Nanoelectronics, and IMEC’s work forms the basis of Intel’s new patent.It is important to note that not all approved patents have a chance to turn into real products or manufacturing technologies.Figure | stacking plan and cross section of the plate type fork transistor (source: United States patent database FPO) at present, cannot decide whether Intel will stack type fork plate transistor used its 2 nm technology, and Intel also is not the performance of the proposed fork piece of transistors made any statement or prediction.But now that Intel has filed a patent for a stacked fork-plate transistor, it suggests that it has a point.After all, the company knows more about the technology’s feasibility than the public does.For decades, Intel has named its chip process nodes in digitally decrement units of size — the distance between the gates — such as Ghana meters.The company recently changed the naming to better reflect the transition to a new era.Intel will name the next node after Intel 3 as Intel 20A and launch the process in 2024.20A is 2nm, and A stands for Angstrom.In addition to the new node naming, Intel said it will make two major breakthrough improvements to the 20A.In this process node, Intel will replace the FinFET transistor technology with a new GAA RibbonFET (Gate-all-around RibbonFET) transistor architecture and use PowerVia power supply technology.In addition, Intel also announced some new improvements to the Intel 20A that will give the Intel 18A a boost.Combined with Intel’s new patent on transistor architecture, the new improvement to the Intel 20A May be the use of stacked fork-plate transistors.- End – reference: